Informatics Publishing Limited

Abstract

FIR filter finds an extensive application in mobile communication. An efficient design of FIR filter makes it suitable for high speed mobile applications including software Defined Radio (SDR). In this paper, we propose an improved FIR filter using Vedic multiplier. First, high speed Vedic multiplier is designed and implemented using the technique of ancient Indian Vedic mathematics has been proposed to improve the performance of multiplier. Vedic mathematics has the distinctive technique of calculations based on 16 sutras. Among the 16 sutras, Urdhva Triyagbhyam has proved to provide better efficiency of the multiplication. Urdhva Triyagbhyam is the most efficient Sutra, giving minimum delay for all categories of numbers, like small or large. Using these sutra middle products are generated parallely and eliminates unnecessary multiplication steps that are done with zeros. The elimination of zeros increases the speed of the multiplier. Using Urdhva Triyagbhyam sutra,e 4x4, 8x8, 16x16 and 32x32 bit multiplier has been designed using verilog HDL and implemented on Spartan 3E FPGA kit. Finally, FIR Filter has been designed using this Vedic Multiplier. The performance of the proposed FIR filter has been compared with the FIR filter with normal multiplier. The proposed FIR filter achieves 15% improvement in area and 5% improvement in speed.

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